I2C (also referred to as I2C) is a multi-master serial single-ended bus used for attaching low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic devices. The I2C bus includes a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for devices: master and slave. A master device is a node that generates the clock and initiates communication with slave devices. A slave device is a node that receives the clock and responds when addressed by the master device.
I3C is a sensor interface proposed by the MIPI Alliance for sensor integration with mobile devices, and embedded system applications. The MIPI I3C specification defines a two-pin interface that is intended to be backward compatible with legacy I2C buses. However, there are challenges in implementing some aspects of the I3C over legacy I2C buses.
Current I3C (latest v0.8 r04) does not provide “byte enable” mechanism in any of the three HDR (high data rate) modes (DDR, TSL, or TSP); only 16-bit per word transfer is supported in a HDR mode.
Camera system, especially newly developed CCS (camera command set) defines byte level registers, and requires byte level register transfer. For example if there are two registers A and B, where both are 8-bit registers and are located in adjacent addresses (e.g., address 0x0004 for A and address 0x0005 for B), HDR cannot be used when the host needs to write only to register B. The host has to use slow SDR (single data rate) mode. Also, since most register access should be done in bulk, meaning multiple registers being accessed in burst, in HDR to save time and power, and target registers often contain different sizes, 8-bit, 16-bit, 32-bit, or larger, “on-the-fly” byte enable scheme is desired in order to “mask” or “skip” certain registers to be written while others are written in bulk.
Therefore, solutions are needed that support I3C features over a legacy I2C bus.